1. Field of the Invention
This invention relates to a semiconductor device, and more particularly, to a dynamic semiconductor memory device comprising a self-refresh circuit and a refresh control method thereof.
2. Description of Related Art
In the manner which is well known in the art, a dynamic random access memory (which will later be also called “DRAM”) is a dynamic semiconductor memory device comprising a plurality of memory cells each of which comprises a switching transistor and a data storing capacitor. Therefore, the DRAM becomes widespread as a semiconductor memory adequate for integration in a semiconductor substrate.
In the DRAM, inasmuch as a data signal is held by the capacitor, it is necessary for “refresh operation” so as to periodically amplify the data signal stored in the capacitor to rewrite it. In other words, electric charges charged in the capacitor gradually discharge by a leak current and eventually data disappears. Therefore, it is necessary to carry out rewrite (refresh) for a memory cell each a constant time interval. The constant time interval is called “a refresh interval”.
In the DRAM, an address of the memory cell is indicated by (row×column) and on specifying an address through an address bus, the address signal is delivered by dividing it into a row address and a column address without delivering at a time. In this event, a control signal for passing bits of the row address to the DRAM through the address bus is called a row address strobe signal /RAS while a control signal for passing bits of the column address to the DRAM is called a column address strobe signal /CAS. In addition, normally, in a state where the row address strobe signal /RAS is produced for outputs of the row address, the column address strobe signal /CAS is produced for outputs of the column address.
In the refresh operation, for example, by producing the row address strobe signal /RAS with the column address strobe signal /CAS is produced for the DRAM, all of the memory cells on a row (a word line) selected (designated) by the row address are simultaneously refreshed. Whenever the column address strobe signal /CAS and the row address strobe signal /RAS are inputted at the above-mentioned timing, the row is successively shifted to refresh the memory cells in turn.
Normally, the refresh operation for one cycle is carried out for a duration until the leading edge of the row address strobe signal /RAS from the falling edge thereof after a refresh address is obtained from a refresh address counter. This duration is called a “refresh duration”. Normally, a normal operation duration follows after the refresh duration. A duration obtained by adding the refresh duration with the normal operation duration is the above-mentioned “refresh interval”.
In recent years, most of the DRAMs have a function which can carry out the refresh operation without requiring a refresh control from an outside. This function is generally called a “self-refresh function”. That is, the self-refresh function adopts a method of generating, inside of a chip, not only the refresh address but also the row address strobe signal /RAS. This method is called a “self-refresh method”. In the self-refresh method, refresh of a memory cell array is carried out by automatically generating a refresh request signal by an internal refresh timer and by automatically generating a RAS-based signal inside the chip.
In addition, a refresh period corresponds to a time length until one row in the memory cell array is next refreshed from being refreshed once.
Various dynamic semiconductor memory devices comprising such a refresh function are already proposed.
By way of illustration, Japanese Unexamined Patent Application Publication of Tokkai No. Hei 6-124587 or JP-A 6-124587 (which will be also called Patent Document 1), which corresponds to U.S. Pat. No. 5,321,662, discloses an improved dynamic random access memory (DRAM) having self refresh mode. In the DRAM disclosed in Patent Document 1, at an initial duration and/or a final duration of a self-refresh duration, a concentrated refresh using a refresh clock signal having a short period is carried out for all rows in a memory cell array.
In addition, Japanese Unexamined Patent Application Publication of Tokkai No. Hei 9-7367 or JP-A 9-7367 (which will be also called Patent Document 2) discloses a refresh apparatus for DRAM which is capable of decreasing power consumption and of shorting the time required for mode transition from an auto-refresh mode to a self-refresh mode in the DRAM.
On the other hand, in order to make a semiconductor integrated circuit operate at a low voltage, a technique for reducing the increase of a standby current which occurs in a case of lowering a threshold value of a transistor is known. Such a technique is called a sub threshold current reduction circuit (SCRC) in this field. Such a SCRC is, for example, disclosed in Japanese Unexamined Patent Application Publication of Tokkai No. Hei 5-210976 or JP-A 5-210976 (which will be also called Patent Document 3).
Conventionally, in the DRAM used in a portable equipment in a cellular phone or the like, a power supply circuit operable at a low voltage and a low power consumption are required. Under a such request, in order to reduce a current on standby, the sub threshold current reduction circuit (SCRC) is applied to a command decoder, a row-based control circuit, a column-based control circuit, and so on. However, among these circuits, the row-based control circuit carries out operation on the self-refresh operation also. The row-based control circuit activates a word line row by row in turn to refresh memory cells connected to the word line. In this event, in a conventional DRAM, the row-based control circuit is activated from a standby state and refreshes the memory cells by activating the word line only one row, and the row-based control circuit is tuned back to the standby state after each refresh completes. Accordingly, the DRAM periodically switches a standby state and an active state every when the word line is refreshed row by row. As a result, the conventional DRAM is disadvantageous in that it is impossible to contrarily reduce a self-refresh current due to charge and discharge of the sub threshold current reduction circuit (SCRC) by switching of activation (active state)/inactivation (standby state) of the row-based control circuit.